1. Field of the Invention
The present invention relates to a system Large Scale Integration (a System LSI) formed on a single semiconductor chip, in which a micro processing unit (a MPU) and a control LSI that may operate independently are formed.
2. Description of the Related Art
FIG. 1 is a diagram showing the configuration of a conventional LSI system. In FIG. 1, the reference number 1 designates a MPU having various kinds of units such as a CPU 3, and the reference number 2 denotes a control LSI having various kinds of units such as a data interface circuit, that may operate independently from the operation of the CPU 1. Hereinafter, this control LSI is referred to as a Hard Disk Controller (HDC). The reference number 3 indicates the CPU in the MPU 1, the reference number 4 designates a code interface unit (hereinafter, referred to as a CIU) for reading program codes stored in a Read Only Memory (ROM) 7 or a Static Random Access memory (SRAM) 8, the reference number 5 denotes a ring buffer as a FIFO buffer for storing the program code read from the ROM 7 or the SRAM 8, and the reference number 6 designates a Data Interface Unit (hereinafter referred to as a DIU) for reading data stored in the ROM 7 or the SRAM 8 or a register 9 and for writing data into the ROM 7 or the SRAM 8 or the register 9. The reference numbers 7, 8, and 9 denote the ROM, the SRAM, and the register, respectively. The reference number 10 designates a control Unit for the HDC 2 (hereinafter referred to as a HDC13 CU). The reference number 11 denotes a data interface circuit for accessing a ROM 13, a SRAM 14, a register group 15 including a plurality of registers such as a register 15a and a register 15b, and a DRAM 16. The reference number 12 indicates a DRAM controller (hereinafter referred to as a DRAMC) for controlling operation of the DRAM 16. The reference numbers 13, 14, 15, 15a, and 15b designate the ROM, the SRAM, the register group, the register, and the register, respectively. The reference number 16 denotes the DRAM, and the reference number 17 indicates a bus group through which data and control signals are transferred among various kinds of units described above in both the MPU 1 and the HDC 2.
FIGS. 2 and 3 are flow charts each showing the operation of the conventional system LSI shown in FIG. 1.
The description will be given of the operation of the conventional system LSI.
First, a fetch operation of program codes performed by the CPU 3 in the MPU 1 for fetching program codes stored in one of the memories such as the ROM 13 and the SRAM 14 in the HDC 2 will be explained.
The CPU 3 outputs a branch request signal RCLR and a branch address AD_CPU to the CIU 4 when the address of the program is branched. When receiving the branch request signal RCLR and the branch address AD_CPU transferred from the CPU 3, the CIU 4 outputs the branch address AD_CPU to the code address bus C_AD. In addition to this, the CIU 4 outputs a code read-out signal CRE to a bus (see FIG. 4). When the branch address AD_CPU indicates a memory field in the ROM 13 in the HDC 2, for example, the ROM 13 in the HDC 2 outputs a program code corresponding to the address to a code bus CB (See FIG. 4).
Thereby, the CIU 4 may input the program code through the code bus CB, and outputs the program code to the ring buffer 5. The ring buffer 5 stores the program code into an empty field indicated by a pointer of the ring buffer 5. The CIU 4 then increments the pointer indicating the memory field in the ring buffer 5, automatically, and continues the fetch operation to the ROM 13 unless the ring buffer 5 has an empty memory field in which no data item is stored. Hereinafter, the above operation will be referred to as a code pre-fetch operation.
In addition, when receiving the code request signal ROPC transferred from the CPU 3, the CIU 4 outputs program codes stored in the ring buffer 5 to the CPU 3 through a bus OPC_BUS. The CIU 4 performs this operation independently from the pre-fetch operation. Hereinafter the above operation will be referred to as a code output operation. That is, when receiving the code request signal ROPC from the CPU 3, the CIU 4 outputs program codes stored in the ring buffer 5 by the number of predetermined memory fields. This ring buffer 5 is a FIFO memory where a first inserted data item is output first.
When receiving the program codes from the CIU 4, the CPU 3 decodes the program codes received, and then executes instructions obtained by this decoding operation.
Because the CIU 4 may perform the code pre-fetch operation and the code output operation in parallel, the CPU 3 gets the program-codes stored in the memories such as the ROM 13, the SRAM 14 through the ring buffer 5 in the CIU 4 and may execute the instructions generated by the decoding operation for the program codes.
The description will be given of the data read operation by the HDC 2 from the memories such as the ROM 7, the SRAM 8, and the register 9 in the MPU 1.
First, the HDC_CU 10 stores in the register 15a (Step ST1) addresses indicating data fields to be required (In this section, the address to be required indicate memory fields in the register 9 for easy explanation) and data informing that the memory access request signal transferred in the Step ST2 (see FIG. 2) is a data read-out request signal for requesting a data read operation. In this case, it is possible for the CPU 3 to recognize the memory access request transferred from the HDC 2 by the following manner.
That is, the CPU 3 reads data stored in the register 15a at regular time intervals. When the data in the register 15aindicates the memory access request during the periodical data read operation, the CPU 3 recognizes the occurrence of the memory access request.
After Step ST 1, because the HDC 2 can not directly access the memories such as the ROM 7, the SRAM 8, and the register 9 in the MPU 1, the HDC 2, that is, because the HDC 2 has no interface circuit for external memories such as the ROM 7, the SRAM 8, and the register 9 in the MPU 1, the HDC_CU 10 in the HDC 2 generates and outputs the memory access request signal to the CPU 3 (see Step ST2).
When receiving the memory access request signal from the HDC_CU 10, the CPU 3 outputs a data read request signal RDR to the DIU 6, and further an address indicating the register 15a in the HDC 2 onto the bus AD_CPU, simultaneously. (In this case, it is determined in advance that the CPU 3 reads data stored in the register 15a when receiving the memory access request signal.)
When receiving the data read request signal RDR transferred from the CPU 3 and the address indicating the register 15a through the bus AD_CPU, the DIU 6 outputs this address to the data address bus D_AD and a data read-out signal DRE on a bus DRF (see FIG. 5).
When receiving the data read-out signal DRE, the register 15a outputs the data stored therein to a data bus DB (see FIG. 5). This data from the register 15a includes an address indicating the register 9 and information indicating that this memory access request signal is a data read-out request signal.
The DIU 6 gets the data through the data bus DB transferred from the register 15a temporarily (see FIG. 5) and then outputs the data to the CPU 3 through the bus D_BUS. Thereby, the CPU 3 obtains both the data read request from the HDC 3 and the address indicating a target data item to be read. When receiving this target address, the CPU 3 outputs both the data read request signal RDR to the DIU 6 through the bus and the target address indicating the register 9 in the MPU 1 through the bus AD_CPU, simultaneously.
When receiving the data read request signal RDR transferred from the CPU 3 and the target address indicating the register 9 through the bus AD_CPU, the DIU 6 outputs address indicating the target address indicating the register 9 to the data address bus D_AD and the data read-out signal DRE to the bus (see FIG. 5).
When receiving the target address indicating the register 9 and the data read-out signal DRE, the register 9 outputs the data stored therein (and that is the data to be required by the HDC 2) to the data bus DB.
After the register 9 outputs the data, the DIU 6 gets this data through the data bus DB, temporarily (see FIG. 5), and transfer the data to the CPU 3 (see Step ST4).
When getting the data through the data bus D_BUS, the CPU 3 outputs a data write signal RWD to the DIU 6, and also outputs an address indicating the register 15b in the HDC 2 through the bus AD_CPU, simultaneously (In this case, it is designed in advance that the CPU 3 writes the data into the register 15bwhen reading the data in response to the read request from the HDC 2.).
When receiving the data write request signal RDW from the CPU 3 through the bus and the address indicating the register 15b through the bus AD_CPU, the DIU 6 outputs the address indicating the register 15b to the data address bus D_AD and the data that has been output to the CPU 3 to the data bus DB, and also outputs the data write-in signal DWE, simultaneously (see FIG. 6).
When receiving the address through the data address bus D_AD and the data through the data bus DB and the data write-in signal DWE, the register 15b stores the data therein (Step ST5).
The HDC_CU 10 reads the data stored in the register 15 under the control of the data interface circuit 11. Thus, the HDC_CU 10 obtains the data stored in the register 9 in the MPU 1 (Step ST6).
Hereinafter, the description will be given of the operation to re-write data stored in the memories such as the ROM 7, the SRAM 8, and the register 9 in the MPU 1.
First, the HDC_CU 10 in the HDC 2 stores into the register 15a following data items:
a data item to be written into the memory;
an address indicating a target memory (it is assumed that the address indicating the target memory is the address indicating the register 9 for brevity); and
information indicating that the memory access request signal output in Step ST12 is a data write request signal.
Because the HDC 2 can not directly access the memories in the MPU 1, the HDC_CU 10 in the HDC 2 generates and outputs the memory access request signal to the CPU 3 when the HDC 2 writes data to the memories in the MPU 1 (Step ST12).
When receiving the memory access request signal from the HDC_CU 10, the CPU 3 outputs the data read request signal RDR to the DIU 6, and outputs an address indicating the register 15a in the HDC 2 through the bus AD_CPU, simultaneously. (In this case, it is assumed in advance that the CPU 3 reads the data stored in the register 15a when receiving the memory access request signal.)
When receiving the data read request signal RDR from the CPU 3 and the address indicating the register 15a through the bus AD_CPU, the DIU 6 outputs the address indicating the register 15a to the data address bus D_AD and also outputs the data read-out signal DRE to the bus DRF (see FIG. 5).
Then, when receiving the address indicating the register 15a and the data read-out request signal DRE, the register 15agenerates and outputs to the data bus DB following data items:
the address stored therein indicating the target memory (in this case, that is the address indicating the register 9);
data informing that this memory access request signal is the data write request signal; and
data to be written into the register 9 (see FIG. 5).
After the register 15a outputs the data on the data bus DB, the DIU 6 gets the data through the data bus DB (see FIG. 5) and then outputs the data to the CPU 3 through the bus D_BUS.
Thereby, the CPU 3 can get the write request from the HDC 2, the address indicating the target memory to which data will be written, and the write-in data to be written into the register 9 (Step ST13).
When receiving the data, the CPU 3 outputs the address indicating the register 9 in the MPU 1 to the bus AD_CPU, and data write request signal RDW, simultaneously.
When receiving the data write request signal RDW transferred from the CPU 3 and the address indicating the register 9 through the bus AD_CPU, the DIU 6 outputs the address indicating the register 9 to the bus D_AD and the write-in data that has been obtained from the CPU 3 through the bus D_BUS, and outputs the data write-in signal DWE (see FIG. 6).
When receiving the address indicating the register 9 and the write-in data and the data write-in signal DWE, the register 9 gets the write-in data through the data bus DB and stores it therein (step ST14).
Because the conventional system LSI has the configuration and the function described above, for example, when the CPU 3 in the MPU 1 reads program codes stored in the memory such as the ROM 13 in the HDC 2, it must be required for the CPU 3 to read the program codes through the CIU 4 in the MPU 1. Hence, the conventional system LSI has a drawback that the speed of the memory accessing to the memories in the HDC 2 becomes low when comparing that the CPU 3 reads the data stored in the memory in the MPU 1.
The description will be given of the reason for the delay of the memory accessing in the conventional system LSI.
The CIU 4 in the MPU 1 has been optimized to access the memories in the MPU 1 at a high speed rate. On the other hand, the HDC_CU10 in the HDC 2 has been optimized to access the memories in the HDC 2 at the high speed rate. Accordingly, the accessing speed in the former becomes lower than the later:
The CIU 4 in the MPU 1 fetches data stored in the memories in the HDC 2; and the CIU 4 in the MPU 1 fetches data stored in the memories in the MPU 1.
In order to avoid this drawback, it is acceptable for the CIU 4 in the MPU 1 to access data at a high speed rate by re-designing the memories in the HDC 2. However, this method causes a new drawback since it becomes impossible for the HDC_CU 10 in the HDC 2 to access the memories in the HDC 2 at a maximum speed rate. This causes a decrease in the performance of the entire system LSI.
On the other hand, it is also acceptable to change the function of the CIU 4 in the MPU 1 so that the memories in the HDC 2 are accessed at a high speed rate. However, this method causes a drawback since it becomes impossible for the CIU 4 in the MPU 1 to access the memories in the MPU 1 at the maximum speed rate. Accordingly, this also causes a decrease in the performance of the entire of the conventional LSI system.
In addition, the conventional system LSI has another drawback that the CIU 4 in the MPU 1 can not access the dedicated memory such as the DRAM 16 for the HDC 2. The reason for this drawback is that the MPU 1 has no DRAM controller. In order to eliminate the drawback, it is acceptable for the MPU 1 to incorporate a DRAM controller. This causes to increase the area of the semiconductor chip, on which the MPU 1 and the HDC 2 are formed, by the area of the added DRAM controller. Even if the DRAM controller is added in the MPU 1 formed on the semiconductor chip, the former drawback still remains that the accessing speed to the memories incorporated in the different devices becomes low.
In addition, because the conventional system LSI does not incorporate any interface circuit for external memories observed from the HDC 2, it is impossible for the HDC_CU 10 in the HDC 2 to directly access the memories in the MPU 1 when the HDC_CU 10 in the HDC 2 reads data stored in the memories in the MPU 1. Accordingly, the HDC_CU 10 in the HDC 2 generates and outputs the memory access request signal to the CPU 3 in the MPU 1 in order to indirectly read desired data. That is, the CPU 3 reads the desired data through the DIU 6 in the MPU 1 and writes the desired data to the register in the HDC 2 and the HDC_CU 10 then gets the desired data through the register in the HDC 2. This therefore causes that the EDC 2 can not read the desired data stored in the different devices at a high speed rate.
In order to eliminate the drawback involved in the conventional system LSI described above, it is acceptable to incorporate an additional DIU in the HDC 2 in order to read the memory in the MPU 1. However, this method has a drawback that the entire area of the semiconductor chip on which the MPU 1 and the HDC 2 are mounted is increased by the area of the additional DIU. Further, the data write accessing to the memories in the MPU 1 by the HDC 2 has a drawback that it is impossible to write data into the memories in the MPU 1 at a high speed rate because the CPU 3 controls the data write access request transferred from the MPU 1, like the data read accessing described above.
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a system LSI capable of reading program codes stored in memories incorporated in a control LSI such as a Hard Disc Controller by a CPU in a MPU at a high speed rate.
In addition, it is another object of the present invention is to provide a system LSI capable of reading data in memories in a MPU by a control LSI at a high speed rate.
Further, it is another object of the present invention is to provide a system LSI capable of writing data in memories in a MPU by a control LSI at a high speed rate.
In accordance with a preferred embodiment of the present invention, a system LSI comprises a MPU and a control LSI. The MPU has a CPU. The control LSI comprises a plurality of memories and a code interface circuit. The code interface circuit receives addresses transferred from the CPU, decodes the addresses, accesses the memories when a decoding result of the addresses indicates memory fields in the memories, reads program codes stored in the memories according to the decoding result of the addresses, and outputs the program codes to the CPU.
In the system LSI as another preferred embodiment of the present invention, the memories includes a DRAM, and the code interface circuit in the control LSI comprises a DRAM control circuit to directly accessing the DRAM.
In the system LSI as another preferred embodiment of the present invention, the code interface circuit comprises a ring buffer to sequentially store the program code that have been read from the memories, and the code interface circuit continues a readout operation of the program codes from the memories unless the ring buffer has empty memory fields.
In accordance with another preferred embodiment of the present invention, a system LSI comprises a MPU having memories, and a control LSI. The MPU comprises a data interface circuit for performing data accessing to the memories when receiving addresses addressing the memories and a data access request signal. The control LSI comprises a control circuit, an access circuit for receiving addresses and an access request signal transferred from the control circuit, for decoding the addresses, and for outputting to the data interface circuit the addresses and the access request signal when a decoding result of the addresses indicates memory fields in the memories in the MPU. In the system LSI, the data interface circuit performs a data access operation to the memories according to the addresses and the access request signal transferred from the access circuit, and then transfers data items as an execution result of the data access operation to the access circuit.
In the system LSI as another preferred embodiment of the present invention, when the control circuit outputs addresses and a data read access request signal as the access request signal, the access circuit receives and decodes the addresses, and outputs the addresses and the data read access request signal to the data interface circuit when a decoding result of the addresses indicates memory fields in the memories. Further, the data interface circuit receives the addresses and the data read access request signal transferred from the access circuit, and reads data items from the memories according to the addresses and the data read access request signal, and then outputs the data items read to the access circuit.
In the system LSI as another preferred embodiment of the present invention, when the control circuit outputs addresses, write-in data to be written, and a data write access request signal as the access request signal, the access circuit receives and decodes the addresses, and outputs the addresses, the write-in data, and the data write access request signal to the data interface circuit when a decoding result of the addresses indicates memory fields in the memories. In addition, the data interface circuit receives the addresses, the write-in data, and the data write access request signal transferred from the access circuit, and writes the write-in data to the memories according to the addresses and the data write access request signal.